49497BR
USA - California - Mountain View/Sunnyvale, USA - Massachusetts - Boston, USA - Massachusetts - Boxborough, USA - Massachusetts - Burlington, USA - Massachusetts - Marlboro
Job Description and Requirements
FPGA group in Synopsys delivers a number of products such as Synplify Pro, Synplify Premier, ProtoCompiler, Certify and Identify. These products are widely used in the industry for implementation of FPGA designs, prototyping and debugging of ASICs using FPGAs. Logic synthesis software, which is part of Synplify Pro and Synplify Premier products, is the industry standards for producing high[1]performance, cost-effective FPGA designs. Its unique Behavior Extracting Synthesis Technology (BEST) performs optimization at a high level first, before synthesizing the RTL code into specific FPGA logic. This approach allows for superior optimization across the FPGA, provides fast runtimes and support for very large designs. Looking for a Senior R&D engineer in ProtoCompiler R&D with a specialization in Static Timing Analysis to join our team in Sunnyvale/Marlborough.
Roles and responsibilities include:
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Stay Connected:
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
#LI-MS
Job Category
Engineering
Country
United States
Job Subcategory
R&D Engineering
Hire Type
Employee
Base Salary Range
$130,000 - $196,000